View AT49BV4096A_58183.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* * * *
2.7V to 3.6V Read/Write Operation Fast Read Access Time - 120 ns Internal Erase/Program Control Sector Architecture - One 8K Words (16K bytes) Boot Block with Programming Lockout - Two 4K Words (8K bytes) Parameter Blocks - One 240K Words (480K bytes) Main Memory Array Block Fast Sector Erase Time - 10 seconds Byte-by-Byte or Word-By-Word Programming - 30 s Typical Hardware Data Protection DATA Polling For End Of Program Detection Low-Power Dissipation - 25 mA Active Current - 50 A CMOS Standby Current Typical 10,000 Write Cycles
* * * * * *
Description
The AT49BV004(T) and AT49BV4096A(T) are 3-volt, 4-megabit Flash Memories organized as 524,288 words of 8 bits each or 256K words of 16 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 120 ns with power dissipation of just 67 mW at 2.7V read. When deselected, the CMOS standby current is less than 50 A. The device contains a user-enabled "boot block" protection feature. Two versions of the feature are available: the AT49BV004/4096A locates the boot block at lowest order addresses ("bottom boot"); the AT49BV004T/4096AT locates it at highest order addresses ("top boot"). To allow for simple in-system reprogrammability, the AT49BV004(T)/4096A(T) does not require high input voltages for programming. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV004(T)/4096A(T) is performed by first erasing a block of data and then programming on a byte-by-byte or word-by-word basis. (continued)
4-Megabit (512K x 8/ 256K x 16) CMOS Flash Memory AT49BV004 AT49BV004T AT49BV4096A AT49BV4096AT Preliminary
Pin Configurations
Pin Name A0 - A18 CE OE WE RESET RDY/BUSY VPP I/O0 - I/O14 I/O15(A-1) BYTE NC Function Addresses Chip Enable Output Enable Write Enable Reset
Ready/Busy Output Optional Power Supply for Faster Program/Erase Operations Data Inputs/Outputs I/O15 (Data Input/Output, Word Mode) A-1 (LSB Address Input, Byte Mode) Selects Byte or Word Mode No Connect
Rev. 1139A-09/98
1
ATBV4096A(T) SOIC (SOP)
*NC/VPP NC A17 A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET WE A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC
AT49BV4096A(T) TSOP Top View Type 1
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE RESET *NC/VPP NC NC NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE GND I/O15 / A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 I/O8 I/O0 OE GND CE A0
AT49BV004(T) TSOP Top View Type 1
A16 A15 A14 A13 A12 A11 A9 A8 WE RESET *NC/VPP RDY/BUSY A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 GND NC NC A10 I/O7 I/O6 I/O5 I/O4 VCC VCC NC I/O3 I/O2 I/O1 I/O0 OE GND CE A0
*Standard device is a NC. Please contact Atmel for VPP option.
The device is erased by executing the erase command sequence; the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections, the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of 10,000 cycles. The 8K word boot block section includes a reprogramming lock out feature to provide data integrity. This feature is enabled by a command sequence. Once the boot block programming lockout feature is enabled, the data in the boot block cannot be changed when input levels of 3.6 volts or less are used. The boot sector is designed to contain user secure code.
For the AT49BV4096A(T), the BYTE pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic "1" or left open, the device is in word configuration, I/O0 - I/O15 are active and controlled by CE and OE. If the BYTE pin is set at logic "0", the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and controlled by CE and OE. The data I/O pins I/O8 - I/O14 are tri-stated and the I/O15 pin is used as an input for the LSB (A-1) address function. An optional VPP pin is available to improve program/erase times. Please contact Atmel for more information.
2
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
AT49BV004(T) Block Diagram
VCC VPP GND OE WE CE RESET ADDRESS INPUTS
INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING MAIN MEMORY (480K BYTES) PARAMETER BLOCK 2 8K BYTES PARAMETER BLOCK 1 8K BYTES BOOT BLOCK 16K BYTES INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING AT49BV004 AT49BV004T
DATA INPUTS/OUTPUTS I/O0 - I/O7
DATA INPUTS/OUTPUTS I/O0 - I/O7
CONTROL LOGIC
Y DECODER X DECODER
7FFFF 08000 07FFF 06000 05FFF 04000 03FFF 00000
BOOT BLOCK 16K BYTES PARAMETER BLOCK 1 8K BYTES PARAMETER BLOCK 2 8K BYTES MAIN MEMORY 480K BYTES
7FFFF 7C000 7BFFF 7A000 79FFF 78000 77FFF 00000
AT49BV4096A(T) Block Diagram
AT49BV4096A AT49BV4096AT
VCC VPP GND OE WE CE RESET ADDRESS INPUTS
DATA INPUTS/OUTPUTS I/O0 - I/O7 - I/O0 - I/O15
DATA INPUTS/OUTPUTS I/O0 - I/O7 - I/O0 - I/O15
CONTROL LOGIC
INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING MAIN MEMORY (240K WORDS) PARAMETER BLOCK 2 4K WORDS PARAMETER BLOCK 1 4K WORDS BOOT BLOCK 8K WORDS
INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING
Y DECODER X DECODER
3FFFF 04000 03FFF 03000 02FFF 02000 01FFF 00000
BOOT BLOCK 8K WORDS PARAMETER BLOCK 1 4K WORDS PARAMETER BLOCK 2 4K WORDS MAIN MEMORY (240K WORDS)
3FFFF 3E000 3DFFF 3D000 3CFFF 3C000 3BFFF 00000
Device Operation
READ: The AT49BV004(T)/4096A(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table (I/O8 - I/O15 are don't care inputs for the command codes). The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the 3
device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. When a high level is reasserted on the RESET pin, the device returns to the Read or Standby mode, depending upon the state of the control inputs. By applying a 12V 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if the boot block program lockout feature has been enabled (see Boot Block Programming Lockout Override section). ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased state of memory bits is a logical "1". The entire device can be erased by using the Chip Erase command or individual sectors can be erased by using the Sector Erase commands. CHIP ERASE: The entire device can be erased at one time by using the 6-byte chip erase software code. After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time to erase the chip is tEC. If the boot block lockout has been enabled, the Chip Erase will not erase the data in the boot block; it will erase the main memory block and the parameter blocks only. After the chip erase, the device will return to the read or standby mode. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into four sectors that can be individually erased. There are two 4K word parameter block sections, one boot block, and the main memory array block. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. Whenever the main memory block is erased and reprogrammed, the two parameter blocks should be erased and reprogrammed before the main memory block is erased again. Whenever a parameter block is erased and reprogrammed, the other parameter block should be erased and reprogrammed before the first parameter block is erased again. Whenever the boot block is erased and reprogrammed, the main memory block and the parameter blocks should be erased and reprogrammed before the boot block is erased again. BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical "0") on a byte-by-byte or word-by-word basis. Programming is accomplished via the internal device command register and is a 4 bus cycle operation. The device will automatically generate the required internal program pulses. Any commands written to the chip during the embedded programming cycle will be ignored. If a hardware reset hap-
pens during programming, the data at the location being programmed will be corrupted. Please note that a data "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 03FFFH for the AT49BV004; 7C000H to 7FFFFH for the AT49BV004T; 00000H to 01FFFH for the AT49BV4096A; and 3E000H to 3FFFFH for the AT49BV4096AT. Once the feature is enabled, the data in the boot block can no longer be erased or programmed when input levels of 5.5V or less are used. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from the following address location will show if programming the boot bloc k is lock ed o ut--00002H for A T49 BV004 and AT49BV4096A; 7C002 for the AT49BV004T; and 3E002H for the AT49BV4096AT. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been enabled and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts during the entire chip erase, sector erase or word programming operation. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.
4
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV004(T)/4096A(T) features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a "0" on I/O7. Once the program or erase cycle has completed, true data will be read from the device. DATA polling may begin at any time during the program cycle. T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e AT49BV004(T)/4096A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. READY/BUSY: For the AT49BV004(T), pin 12 is an open drain READY/BUSY output pin which provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and it is released at the completion of the cycle. The open drain connection allows for ORtying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV004(T)/4096A(T) in the following ways: (a) V CC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) VCC power on delay: once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE, and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
5
Command Definition (in Hex)(1)
Command Sequence Read Chip Erase Sector Erase Byte/Word Program Boot Block Lockout(2) Product ID Entry Product ID Exit Product ID Exit Notes:
(3) (3)
Bus Cycles 1 6 6 4 6 3 3 1
1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 xxxx Data DOUT AA AA AA AA AA AA F0
2nd Bus Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cycle Addr Data
6th Bus Cycle Addr Data
2AAA 2AAA 2AAA 2AAA 2AAA 2AAA
55 55 55 55 55 55
5555 5555 5555 5555 5555 5555
80 80 A0 80 90 F0
5555 5555 Addr 5555
AA AA DIN AA
2AAA 2AAA
55 55
5555 SA
(4)
10 30
2AAA
55
5555
40
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don't Care) 2. The boot sector has the address range 00000H to 03FFFH for the AT49BV004; 7C000H to 7FFFFH for the AT49BV004T; 00000H to 01FFFH for the AT49BV4096A; and 3E000H to 3FFFFH for the AT49BV4096AT. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses: (A18 - A0) For the AT49BV004 SA = 03XXX for BOOT BLOCK SA = 05XXX for PARAMETER BLOCK 1 SA = 07XXX for PARAMETER BLOCK 2 SA = 7FXXX for MAIN MEMORY ARRAY For the AT49BV004(T) SA = 7FXXX for BOOT BLOCK SA = 7BXXX for PARAMETER BLOCK 1 SA = 79XXX for PARAMETER BLOCK 2 SA = 77XXX for MAIN MEMORY ARRAY SA = sector addresses: (A17 - A0) For the AT49BV4096A SA = 01XXX for BOOT BLOCK SA = 02XXX for PARAMETER BLOCK 1 SA = 03XXX for PARAMETER BLOCK 2 SA = 3FXXX for MAIN MEMORY ARRAY For the AT49BV4096AT SA = 3FXXX for BOOT BLOCK SA = 3DXXX for PARAMETER BLOCK 1 SA = 3CXXX for PARAMETER BLOCK 2 SA = 3BXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on RESET with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
6
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
DC and AC Operating Range
AT49BV004(T)/4096A(T)-12 Operating Temperature (Case) VCC Power Supply Com. Ind. 0C - 70C -40C - 85C 2.7V to 3.6V
Operating Modes
Mode Read Program/Erase
(2)
CE VIL VIL VIH X X X X
OE VIL VIH X(1) X VIL VIH X
WE VIH VIL X VIH X X X
RESET VIH VIH VIH VIH VIH VIH VIL
VPP(6) X 5V 10% X VIL VIL X X
Ai Ai Ai X
I/O DOUT DIN High Z
Standby/Program Inhibit Program Inhibit Program Inhibit Output Disable Reset Product Identification
High Z X High Z
Hardware
VIL
VIL
VIH
VIH
A1 - A18 = VIL, A9 = VH,(3) A0 = VIL A1 - A18 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A18 = VIL A0 = VIH, A1 - A18 = VIL
Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4)
Software(5)
VIH
Notes:
1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V 0.5V. 4. Manufacturer Code: 161FH Device Code: 11H (AT49BV004), 1692H (AT49BV4096A), 10H (AT49BV004T), 1690H (AT49BV4096AT). 5. See details under Software Product Identification Entry/Exit. 6. A VPP pin is optional. Please contact Atmel.
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10 10 50 1 25 0.6 Units A A A mA mA V V V V
Note:
1. In the erase mode, ICC is 50 mA.
7
AC Read Characteristics
AT49BV004(T)/4096A(T)-12 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH tRO Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE,CE or Address, whichever occurred first RESET to Output Delay 0 0 0 800 Min Max 120 120 50 30 Units ns ns ns ns ns ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS ADDRESS VALID
CE t OE CE t OE t DF t t ACC t RO OUTPUT VALID OH
RESET OUTPUT
HIGH Z
Notes:
1. 2. 3. 4.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25C(1)
Typ CIN COUT 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
8
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
AC Word Load Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 10 100 0 0 100 100 10 50 Max Units ns ns ns ns ns ns ns ns
AC Byte/Word Load Waveforms WE Controlled
CE Controlled
9
Program Cycle Characteristics
Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte/Word Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 100 100 0 100 50 10 Min Typ 30 Max Units s ns ns ns ns ns ns seconds
Program Cycle Waveforms
PROGRAM CYCLE OE
CE t WP WE t AS A0-A18 t AH 5555 t DS DATA AA 55 A0 INPUT DATA AA t DH 2AAA 5555 ADDRESS 5555 t WPH t BP
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE t WP WE t AS t AH 5555 t DS DATA AA BYTE/ WORD 0 55 BYTE/ WORD 1 80 BYTE/ WORD 2 AA BYTE/ WORD 3 55 BYTE/ WORD 4 Note 3 BYTE/ WORD 5 t DH 2AAA 5555 5555 2AAA Note 2 t EC t WPH
A0-A18
Notes:
1. 2. 3.
OE must be high only when WE and CE are both low. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under command definitions.) For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
10
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
0
ns
Data Polling Waveforms
WE CE tOEH OE tDH I/O7 A0-A18 tOE HIGH Z tWR
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics.
(2)
Min 10 10
Typ
Max
Units ns ns ns
150 0
ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
11
Software Product Identification Entry(1)
LOAD DATA AA TO ADDRESS 5555
Boot Block Lockout Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 90 TO ADDRESS 5555
LOAD DATA 80 TO ADDRESS 5555
ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5)
LOAD DATA AA TO ADDRESS 5555
Software Product Identification Exit(1)(6)
LOAD DATA AA TO ADDRESS 5555 OR LOAD DATA F0 TO ANY ADDRESS
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
EXIT PRODUCT IDENTIFICATION MODE(4)
LOAD DATA 40 TO ADDRESS 5555
PAUSE 1 second(2) LOAD DATA F0 TO ADDRESS 5555
Notes:
1.
Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don't Care). Boot block lockout feature enabled.
EXIT PRODUCT IDENTIFICATION MODE(4)
2.
Notes:
1.
Data Format: I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex) Address Format: A15 - A0 (Hex), A-1, and A15 - A18 (Don't Care). A1 - A18 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does not remain in identification mode if powered down. The device returns to standard operation mode. Manufacturer Code: 161FH Device Code: 11H (AT49BV004), 1692H (AT49BV4096A), 1692H (AT49BV004T), 1690H (AT49BV4096AT) Either one of the Product ID Exit commands can be used.
2.
3. 4. 5.
6.
12
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
AT49BV004(T) Ordering Information
tACC (ns) 120 ICC (mA) Standby Active 25 0.05 Ordering Code AT49BV004-12TC AT49BV004-12TI 120 25 0.05 AT49BV004T-12TC AT49BV004T-12TI Package 40T 40T 40T 40T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
Package Type 40T 40-Lead, Plastic Thin Small Outline Package (TSOP)
13
AT49BV4096A(T) Ordering Information
tACC (ns) 120 ICC (mA) Active 25 Standby 0.05 Ordering Code AT49BV4096A-12RC AT49BV4096A-12TC AT49BV4096A-12RI AT49BV4096A-12TI 120 25 0.05 AT49BV4096AT-12RC AT49BV4096AT-12TC AT49BV4096AT-12RI AT49BV4096AT-12TI Package 44R 48T 44R 48T 44R 48T 44R 48T Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Commercial (0 to 70C) Industrial (-40 to 85C)
Package Type 44R 48T 44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC) 48-Lead, Plastic Thin Small Outline Package (TSOP)
14
AT49BV004(T)/4096A(T)
AT49BV004(T)/4096A(T)
Packaging Information
44R, 44-Lead, 0.525" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 40T, 40-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Inches and (Millimeters)
*Controlling dimension: millimeters 48T, 48-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 D
*Controlling dimension: millimeters
15

▲Up To Search▲

Price & Availability of AT49BV4096A

	To Download AT49BV4096A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .